There exists a tradeoff relation between the on-resistance (current capacity) and the breakdown voltage of the vertical semiconductor device, which includes electrodes distributed on both major surfaces of the semiconductor chip and a vertical drift region, which makes a current flow in the thickness direction of the semiconductor chip. To reduce the tradeoff relation, the vertical drift region has been provided with an alternating conductivity type structure formed of heavily doped vertical n-type regions and heavily doped vertical p-type regions laminated alternately along the major surfaces of the semiconductor chip. The vertical drift region having the alternating conductivity type structure is depleted quickly. In the peripheral region of the semiconductor device, in which substantially no current flows, depletion layers hardly expand outward or into the deep portion of the semiconductor substrate, since the vertical n-type regions and the vertical p-type regions constituting the alternating conductivity type structure in the peripheral region are doped heavily. Due to the heavily doped vertical ntype regions and the heavily doped vertical p-type regions, the electric field strength in the peripheral region soon reaches the critical value for silicon before the applied voltage reaches the designed breakdown voltage of the device. Therefore, the designed breakdown voltage is not obtained.
For obviating the problem described above, it is preferable to provide the peripheral region with an alternating conductivity type structure doped more lightly than the alternating conductivity type structure in the drift region. Alternatively, it is preferable to provide the peripheral region with an alternating conductivity type structure including vertical n-type regions and vertical p-type regions alternately arranged at a pitch of repeating narrower than the pitch of repeating in the drift region.
FIG. 30 is a top plan view of a conventional vertical MOSFET showing the drift region and the peripheral region (breakdown withstanding region) thereof. FIG. 31 is a vertical cross section taken along line 31xe2x80x9431 of FIG. 30. FIG. 32 is a vertical cross section taken along line 32xe2x80x9432 of FIG. 30. Referring now to these figures, the n-channel vertical MOSFET includes an n+-type drain layer (contact layer) 11 with low electrical resistance, a drain electrode 18 on the back surface (second major surface) of the semiconductor chip and in electrical contact with n+-type drain layer 11, a drift region 22 including a first alternating conductivity type layer formed on n+-type drain layer 11, heavily doped p-type base regions (p-type well regions or channel diffusion regions) 13a formed selectively in the surface portion of the drift region 22, a heavily doped n+-type source region 14 formed selectively in the surface portion of the p-type base region 13a, a polysilicon gate electrode layer 16 above the first major surface of the semiconductor chip with a gate insulation film 15 interposed therebetween, and a source electrode 17 in electrical contact with the p-type base regions 13a and the n+-type source regions 14 via contact holes bored through an interlayer insulation film 19a. The n+-type source region 14 is formed shallowly in the p-type base region 13a shaped with a well such that a double-diffusion MOS region constituting the active region of the device is formed. A p+-type contact region 26 is in the p-type base region 13a. Although not shown in the figures, a gate electrode layer 16 is connected to a gate wiring metal film above the gate electrode layer 16.
The first alternating conductivity type layer in drift region 22 includes first n-type regions 22a and first p-type regions 22b. The first n-type regions 22a and the first p-type regions 22b are shaped with respective layers extending vertically in the thickness direction of the semiconductor chip. The first n-type regions 22a and the first p-type regions 22b are laminated alternately along the major surface of the semiconductor chip. The first n-type regions 22a, with the upper ends thereof are in contact with the sandwiched regions 12e between the p-type base regions 13a, provide a substantial current path in the on-state of the device. The lower ends of the first n-type regions 22a are in contact with the n+-type drain layer 11. The upper ends of the first p-type regions 22b are in contact with the well bottoms of the respective p-type base regions 13a. The lower ends of the first p-type regions 22b are in contact with the n+-type drain layer 11.
The n-channel vertical MOSFET includes also a peripheral region 20 between the surface of the semiconductor chip and the n+-type drain layer 11 and surrounding the drift region 22. The peripheral region 20 includes a second alternating conductivity type layer, including second n-type regions 20a and second p-type regions 20b. The second n-type regions 20a and the second p-type regions 20b are shaped with respective layers extending vertically in the thickness direction of the semiconductor chip. The second n-type regions 20a and the second p-type regions 20b are laminated alternately along the major surface of the semiconductor chip. An oxide film (insulation film) 23 made of a thermal oxide or a phosphorus silica glass (PSG) is formed on the second alternating conductivity type layer in the peripheral region 20 for surface protection and for surface stabilization. To facilitate expanding depletion layers in the second alternating conductivity type layer, the second alternating conductivity type layer is doped more lightly than the first alternating conductivity type layer. Alternatively, the second pitch of repeating P2, namely where a pair of the second n-type region 20a and the second p-type region 20b repeat, is narrower than the first pitch of repeating P1, namely where a pair of the first n-type region 22a and the first p-type region 22b repeat.
The vertical MOSFET shown in FIGS. 30 through 32 has the following problems. Since the outermost first n-type region 22aa of the first alternating conductivity type layer in the drift region 22 is in contact with the innermost p-type region 20bb of the second alternating conductivity type layer, the impurity concentration therein are different from the impurity concentration in the first alternating conductivity type layer or the pitch of repeating thereof is different from the pitch of repeating in the first alternating conductivity type layer, causing charge imbalance between the outermost first n-type region 22aa and the innermost p-type region 20bb. Since none of the outermost first n-type region 22aa and the innermost p-type region 20bb is depleted completely in the off-state of the device, electric field localization is formed in the boundary plane X between the first and second alternating conductivity type layers. Therefore, it is difficult to obtain the designed breakdown voltage. Since the charge imbalance between the outermost first n-type region 22aa and the innermost p-type region 20bb causes larger lowering of the breakdown voltage as the alternating conductivity type layers are designed to be thicker for obtaining a vertical semiconductor device of a higher breakdown voltage class, the alternating conductivity type layer formed in the peripheral region of the device for obtaining a higher breakdown voltage does not work as intended.
Accordingly, there is a need for a semiconductor device, including a drift region formed of an alternating conductivity type layer and a peripheral region formed of an alternating conductivity type layer, which facilitates relaxing the surface electric field mainly in the peripheral region so that a higher breakdown voltage and a higher current capacity may be realized. The present invention addresses this need.
The present invention relates to a vertical power semiconductor structure that is applicable to insulated gate field effect transistors (MOSFET""s), conductivity-modulation MOSFET""s (IGBT""s), bipolar transistors, and such active devices and diodes and such passive devices. Specifically, the present invention relates to vertical power semiconductor devices that can exhibit a high breakdown voltage and a high current capacity.
A semiconductor device according to the present has a semiconductor chip, an active region, a layer with low electrical resistance, a drift region, and a peripheral region. The chip has a first major surface and a second major surface facing opposite to the first major surface. The active region is on the side of the first major surface for actively or passively making current flow. The layer with low electrical resistance can be of a first conductivity type and on the side of the second major surface. The drift region can be between the active region and the layer with low electrical resistance. The drift region provides a vertical drift current path in the ON-state of the semiconductor device and is depleted in the OFF-state of the semiconductor device. The peripheral region is formed around the drift region, between the first major surface and the layer with low electrical resistance. The peripheral region provides substantially no current path in the ON-state of the semiconductor device. The peripheral region is also depleted in the OFF-state of the semiconductor device.
According to one aspect of the present invention, the drift region can have a first alternating conductivity type layer, which can include first regions of the first conductivity type and first regions of a second conductivity type. The first regions can extend perpendicular to the second major surface and are arranged alternately, repeating at a first pitch parallel to the second major surface. The peripheral region can have a second alternating conductivity type layer, which can include second regions of the first conductivity type and second regions of the second conductivity type. The second regions can extend perpendicular to the second major surface and arranged alternately, repeating at the first pitch parallel to the second major surface. The impurity concentration in the second alternating conductivity type layer can be substantially the same as the impurity concentration in the first alternating conductivity type layer. The peripheral region can further include a third alternating conductivity type layer in the surface portion thereof on the side of the first major surface. The third alternating conductivity type layer has third regions of the first conductivity type and third regions of the second conductivity type. The respective third regions can extend perpendicular to the second major surface and arranged alternately parallel to the second major surface, and the impurity concentration in the third alternating conductivity type layer can be lower than the impurity concentration in the first alternating conductivity type layer.
According to another aspect of the present invention, the respective third regions can be arranged alternately, repeating at a second pitch parallel to the second major surface. The second pitch can be narrower than the first pitch.
According to yet another aspect of the present invention, the first alternating conductivity type layer of the drift region can include a first region of the first conductivity type and first regions of the second conductivity type configured as columns standing on lattice points of a first planar polygonal lattice, and repeating at a first pitch, with the first region of the first conductivity type surrounding the first regions of the second conductivity type. Similarly, the second alternating conductivity type layer can include a second region of the first conductivity type and second regions of the second conductivity type configured as columns standing on the lattice points of the first planar polygonal lattice and repeating at a first pitch, with the second region of the first conductivity type surrounding the second regions of the second conductivity type. The impurity concentration in the second alternating conductivity type layer can be substantially the same as the impurity concentration in the first alternating conductivity type layer. Similarly, the third alternating conductivity type layer can include a third region of the first conductivity type and third regions of the second conductivity type configured as columns standing on the lattice points of a second planar polygonal lattice and repeating at a second pitch, with the third region of the first conductivity type surrounding the third regions of the second conductivity type. The second pitch can be narrower than the first pitch.
The first alternating conductivity type layer and the second alternating conductivity type layer can be continuous with each other. The third alternating conductivity type layer can be one half or less as thick as the first alternating conductivity type layer. The third alternating conductivity type layer can be in contact with the first major surface. The third alternating conductivity type layer can extend below the peripheral portion of the active region.
The first regions of the first conductivity type, the first regions of the second conductivity type, the second regions of the first conductivity type, the second regions of the second conductivity type, the third regions of the first conductivity type, and the third regions of the second conductivity type can be configured as stripes extending in a plane parallel to the second major surface.
The direction in which the first regions of the first conductivity type and the first regions of the second conductivity type are arranged alternately can be substantially parallel to or perpendicular to the direction in which the third regions of the first conductivity type and the third regions of the second conductivity type are arranged alternately.
The semiconductor device can further include a channel stopper region of the first conductivity type around the second alternating conductivity type layer and the third alternating conductivity type layer. The channel stopper region can be connected to the layer with low electrical resistance.
The semiconductor device can further include an insulation film covering the third alternating conductivity type layer and a field plate covering at least the inner portion of the third alternating conductivity type layer with the insulation film interposed therebetween.
The semiconductor device can further include one or more rings of the second conductivity type around the active region and on the first major surface side of the third alternating conductivity type layer.